Stress migration, also referred to as stress-induced voiding or cavitation, is a post-fabrication failure mechanism for semiconductor devices. Stress migration causes voids to form in metallization interconnect lines. An open circuit may occur if enough voids accumulate in a location along the interconnect line. An accumulation of voids can also lead to degraded circuit performance through substantially higher resistances.
The voids arise from vacancies in the interconnect metallization. The vacancies form during fabrication processes, such as during deposition and electroplating. For example, an electroplated metal layer is often left with grains. Vacancies are present between the grains. Oftentimes, when the semiconductor device is tested immediately after fabrication, the vacancies remain harmlessly distributed at various positions along the conductors.
Device failures subsequently occur as the vacancies migrate and accumulate to form the voids. The vacancies migrate due to stress gradients arising from different thermal expansion coefficients between the interconnect metal and surrounding dielectric layers. The thermal expansion coefficients of the conductor materials (e.g., aluminum and copper) may be several times greater than the thermal expansion coefficients of the substrate (e.g., silicon) and dielectric materials adjacent the interconnects. The conductors thus expand and contract at a different rate than the nearby semiconductor and dielectric materials during subsequent heating and cooling cycles. The thermal cycles may occur during subsequent fabrication processes or over time as a result of use in the field.
Vias present discontinuities in the stress fields in the conductors. As a result, the vacancies tend to migrate to, and accumulate at, the vias. As more vacancies accumulate at a particular via, a void is formed. Over time, the voids can grow and lead to an open circuit or significant increase in resistance, thereby leading to via failure.
Although the failure of any one individual via may have a low probability of occurring, the likelihood of one via failure on a chip with millions of vias is undesirably high. Thus, circuits often include redundant vias, the theory being that it is sufficiently unlikely that two vias will fail on the same interconnect. However, inserting redundant vias is often complicated or prevented by a lack of space in circuit layouts.